Current trends in multi-core processor implementation scale by
duplicating a single core design many times in a package; however, this
approach can cause inefficient utilization of resources, such as die
space and power. Recent research has proposed asymmetric cores as an
alternative solution. This paper explores the design space for
asymmetric multi-core architectures, and presents a case study and
prototype of one design in which cores implement overlapping, but
nonidentical instruction sets.
We propose fault-and-migrate, which enables the OS to manage hardware asymmetries transparently to applications. Our mechanism traps the fault when a core executes an unsupported instruction, migrates the faulting thread to a core that supports the instruction, and allows the OS to migrate it back when load balancing is necessary. We have also developed three approaches to emulate future asymmetric processors using current hardware. Preliminary evaluation shows that fault-and-migrate enables applications to execute transparently and incurs less than 4% overhead for a SPEC CPU2006* benchmark.
Intel Labs: Tong Li, Paul Brett, Barbara Hohlt, Rob Knauerhase, Sean D. McElderry, and Scott Hahn
Workshop on the Interaction between Operating Systems and Computer Architecture (WIOSCA 2008) http://www.ideal.ece.ufl.edu/main.php?action=wiosca08 PDF